Copper Thieving literally refers to the Thieving of Copper, which is called equal-flow block or electroplating block, and refers to the Copper balance block added to the outer graphics area of multilayer PCBS, PCB assembly auxiliary strip and manufacturing panel auxiliary strip.
What is Copper Thieving for? Balance electroplating current during outer electroplating process in PCB production process to avoid uneven copper thickness of finished products due to inconsistent current in electroplating process. In other words, in the process of electroplating, the electroplating current is taken from the dense area of copper foil, so that the current distribution is more even, that is, to avoid the uneven thickness of finished copper.
These small copper look like copper clad, but is different, it is made up of many very small independent square shape of copper, copper piece each is independent of the monomer, not with other components for electrical connection in the circuit boards, as we know, for example, large area laying copper on the PCB to focus at least 1/10 of the wavelength frequency spacing too hole metallization, Connect to the main 0V reference plane on the PCB.
A large area of suspended copper foil is equivalent to Patch Antenna. As shown in the figure below, the common-mode current on the board easily enters the external electromagnetic radiation of the Antenna, resulting in electromagnetic compatibility problems.
Large area of copper hole play is not enough, high impedance, cause resonance, radiation electromagnetic wave.
In fact, the disadvantages of copper coating PCB with low impedance backflow plane based on high-speed digital signal are greater than the advantages. Note that it is said here [high-speed digital signal mainly] and [low impedance backflow plane], pay attention to this premise, if it is double-layer board or high impedance analog circuit, copper coating is still very beneficial.
For multilayer PCB has low impedance back plane, the high number of digital signal backflow will directly go minimum impedance shortest paths rather than linear distance to the path of least resistance, which is most reflow focused on signal corresponding to the reference plane, go line and the reference plane at a distance of H is smaller, back on the reference plane of the current focus on running with the corresponding area, In other words, the diffusion area of reflux current is relatively small, which can reduce crosstalk. The closer the reflux coupling is, the more the differential mode radiation can be reduced. So, to improve the performance of the surface of EMC optimization method is through reasonable laminated structure design, make the reference for the signal transmission line and plane, as close as possible to return from the low impedance of the reference plane, rather than through the way of laying copper structure also return path to make up for, that is not what happened to copper clad. To cover copper, you also need to make metallized holes to connect to the 0V reference plane, and copper can also form accidental antennas in obscure places. Once played holes, each hole crowding the lining of the already crowded go line space, and the integrity of the main power / 0 v reference plane, was more and more IC pins and go line in layer hole has taken the plane as the screen mesh, plus the outer plane to fill the pile hole, to the detriment of the principal plane of low impedance more. At the same time, improper processing of copper foil, which is too close to the transmission line requiring impedance control in local areas, will also cause impedance mutation of the transmission line, and signal reflection will occur where impedance is discontinuous, leading to signal integrity problems.
Of course, if there are relatively complete copper foils in the outer layer, these copper foils can play a certain shielding role or improve the interlayer capacitance of PCB, which will be helpful to improve EMC performance. However, in the case of high-number digital signals, the outer layer is full of components and fan holes, so it is difficult to form a complete plane.
For the two-layer plate, the distance between wiring and its reference plane is too far. Meanwhile, the 0V reference plane needs wiring, which is difficult to ensure the integrity of the plane. At this time, copper is laid in the spare area of the board and more holes are drilled to connect with the 0V reference to construct a low impedance reflux path, which is very beneficial to improve EMC performance.
For the wiring area of high digital signal with low impedance reference plane, the old Wu will not lay copper on the outer layer. However, if the residual copper rate of the outer layer is too low, such as the BGA area of main control and surrounding DRAM, the density of copper foil is relatively dense, and the copper content in other areas is relatively small. The uneven copper distribution rate is in the electroplating process. The current density flowing through the BGA area is too large, resulting in uneven copper thickness of electroplated products. For example, the uneven copper thickness of the difference line will have a negative impact on impedance control, and the large difference of copper thickness on the BGA pins will also affect the yield of SMT.
The solution is to improve the distribution of the copper foil density balance, the small chess lattice copper is a good choice, of course, also have a plenty of small dot shapes, each of its monomer is far much smaller in physical size of a quarter, it is difficult to form effective radiating antenna, without a reference plane connection hole at 0 v, don't have to use the lining of the crowded go line space, The only thing to note is that there are no impedance control lines on the Thieving underside as these Copper blocks cause impedance discontinuances. Of course, don't go too close to ESD protection.