Wafer manufacturing and chip manufacturing are two steps to make integrated circuits. Wafer manufacturing includes two major steps, ingot manufacturing, and wafer manufacturing. It can be subdivided into the following main processes: polysilicon-single crystal silicon-ingot growth-ingot cutting and inspection-outer diameter grinding ——Slicing—Round edge—Surface grinding—Etching—Flaw removal—Polishing— (Epitaxial—Etching—Flaw removal) —Cleaning—Inspection—Packaging. Chip manufacturing can be roughly divided into several steps: Wafer Fabrication, Wafer Probe, Packaging, Initial Test and Final Test, and other steps.
1. Wafer manufacturing (crystal growth-slicing-edge grinding-polishing-wrapping-shipping)
Figure 1 Crystal
Crystal Growth
Crystal growth requires a highly accurate automated crystal pulling system. Quartz ore is refined by electric arc furnace, chlorinated with hydrochloric acid, and distilled to make high-purity polysilicon, whose purity is as high as 0.99999999999. A small amount of electroactive "dopants" such as arsenic, boron, phosphorus, or antimony are added to the polysilicon obtained by refining quartz ore, and they are melted together in a high-temperature furnace. A long crystal cable is then used as a seed crystal and inserted into the bottom of the molten polysilicon. Then, rotate the cable and slowly pull it out. After cooling, a cylindrical single crystal silicon ingot, that is, a silicon rod is formed. This process is called "crystal growth." Silicon rods are generally 3 feet long and come in 6-, 8-, and 12-inch diameters. After the silicon ingot is ground, polished, and sliced, it becomes the basic raw material for manufacturing integrated circuits-wafers.
Slicing / Edge Grinding / Surface Polishing
Figure 2 ingot slicing
Slicing uses special internal blades to cut silicon rods into thin wafers with precise geometries. Then, the surface and edges of the wafer are polished, ground, and cleaned. The sharp edges of the newly cut wafer are rounded to remove rough scratches and impurities, and a nearly perfect silicon wafer is obtained.
Wrapping / Shipping
After the wafer manufacturing is completed, professional equipment is needed to package and transport these nearly perfect silicon wafers. Wafer Carriers provide semiconductor manufacturers with fast, consistent, and reliable wafer pick-and-place.
2. Deposition
Epitaxial deposition
Figure 3 Wafers and epitaxial wafers
The epitaxial layer is the first layer deposited on a semiconductor wafer. Most modern epitaxial growth depositions use low-pressure chemical vapor deposition (LPCVD) to grow silicon films on silicon substrates. The epitaxial layer is formed of ultra-pure silicon and acts as a buffer layer to prevent harmful impurities from entering the silicon substrate. In the past, bipolar processes generally required the use of epitaxial layers, and CMOS technology was not used. Since the epitaxial layer may enable the use of wafers with a small number of defects, it may be more used on 300mm wafers in the future.
Chemical Vapor Deposition
Figure 4 Chemical Vapor Deposition
Chemical vapor deposition (CVD) is a technique that deposits a mixture on the wafer surface by decomposing gas molecules. CVD produces many non-plasma thermal intermediates. One common aspect is that these intermediates or precursors are all gases. There are many types of CVD technologies, such as thermal CVD, plasma CVD, non-plasma CVD, atmospheric CVD, LPCVD, HDPCVD, LDPCVD, PECVD, etc., which are applied to different aspects of semiconductor manufacturing.
Physical Vapor Deposition
Figure 5 Physical Vapor Deposition
The most common metal interconnect material on a wafer is Al, and a physical vapor deposition (PVD) method is commonly used to prepare metal material films. In the PVD system, the Al target is bombarded with ions, so that Al atoms on the target surface escape with a certain energy, and then deposited on the wafer surface. The PVD is also used to deposit barrier and seed layers, as well as copper films for dual-embedded, interconnects.
3. Photolithography
Figure 6 Photolithography
Photolithography is the process of printing chip circuit patterns on wafers. It is the most critical step in the manufacture of integrated circuits. It accounts for about 35% of the overall manufacturing cost in the entire chip manufacturing process. Lithography is also an important factor that determines the development of integrated circuits following Moore's Law. Without the advancement of lithography technology, integrated circuits will not be able to move from micrometers to deep sub microns and then enter the nanometer era.
The photolithography process transfers the mask pattern to the photoresist on the wafer surface. First, the photoresist processing equipment spin-coats the photoresist onto the wafer surface and then repeats the exposure and development process step by step to form needed graphics on the wafer. The difficulty of a process is usually expressed by the number of masks that a process needs to pass. According to different exposure methods, lithography can be divided into contact type, proximity type, and projection type; According to the number of lithographic planes, there are single-sided alignment lithography and double-sided alignment lithography; Depending on the type of photoresist, there are thin photoresist and thick photoresist. The general lithography process includes pre-processing, leveling, pre-baking, alignment exposure, development, and post-baking. The operations in the process can be adjusted according to the actual situation.
4. Etching
Figure 7 Etching
In the integrated circuit manufacturing process, after mask registration, exposure and development, the required pattern is copied on the resist film, or the electron beam is directly drawn to generate the pattern on the resist film. This pattern is then accurately transferred to the dielectric film (such as silicon oxide, silicon nitride, polysilicon) or metal film under the resist to produce the desired thin layer pattern. The etching is to use chemical, physical, or both chemical and physical methods to selectively remove the part of the thin film layer that is not masked by the resist, so as to obtain a pattern on the thin film that is completely consistent with the resist film. Plasma etch is the ionization of reactive gas to form a plasma under specific conditions. The plasma selectively removes substances from the wafer, and the remaining substances form a chip pattern on the wafer.
5. Ion Implantation
The wafer substrate is a pure silicon material, which is non-conductive or weakly conductive. To have conductivity in the chip, a small number of impurities must be added to the wafer, usually arsenic, boron, and phosphorus. Doping can be done in a diffusion furnace or by ion implantation. Some advanced applications are doped with ion implantation. There are three types of ion implantation: medium current ion implantation, high current / low energy ion implantation, and high energy ion implantation, which are suitable for different application needs.
6. Thermal Processing
Thermal processing is the use of thermal energy to eliminate some of the internal stresses in the object. The applied energy will increase the vibration and diffusion of lattice atoms and defects in the object so that the arrangement of the atoms can be rearranged. Heat processing is a process after the deposition manufacturing process to change the mechanical properties of the deposited film.
At present, there are two main applications of heat treatment technology: One uses ultra-low-k insulators to increase the hardness of porous films, the other uses high-strength nitrides to increase the toughness and tensile strength of the deposited film to improve device performance. In the UV heat treatment reactor, the plasma-enhanced chemical vapor deposition thin film changes the properties of the film through a combination of light and heat. The ultraviolet heat treatment process in the high-strength nitride film makes the connections rearranged and the space contact is better, resulting in the high strength level required to improve the performance of the device.
7. Chemical mechanical polishing (CMP)
One of the keys to the advancement of chip technology is the increase in the number of layers per chip, the increasing number of layers stacked on a chip, and the unevenness of each layer will increase the difficulty of lithographic fine circuit images. The CMP system uses a polishing pad and a chemical abrasive to selectively polish and flattens the deposited layer. CMP includes polysilicon metal dielectric (PMD) planarization, interlayer insulation film (ILD) planarization, and tungsten planarization. CMP is a key technology in copper damascene interconnect technology.
8. Wafer Metrology
In the chip manufacturing process, to ensure that the wafer is processed according to the predetermined design requirements, a large number of inspections and measurements must be confirmed, including the measurement of the line width on the chip, the measurement of the thickness of each layer, the measurement of the surface topography of each layer, and the measurement of each layer. Some electronic performance measurements.
With the continuous development of semiconductor processes and manufacturing technologies, these tests have become an indispensable part to improve mass production and yield. In the copper interconnect process, due to the use of finer line width technology and low-k dielectric materials, more sophisticated test equipment and new test methods need to be developed.
The inspection mainly includes three types: optical inspection, thin-film inspection, and critical dimension scanning electronic inspection (CD-SEM). An important development trend of wafer inspection is the integration of multiple measurement methods in one process equipment.
9. Wafer Inspection (Particles)
Figure 8 Wafer Inspection System
Many steps in the wafer manufacturing process require wafer contamination inspection, such as bare wafer inspection, equipment monitoring (using process equipment to control the particle size deposited on the wafer), and inspection after CMP, CVD, and ion implantation. Usually, such inspections are done before the wafer application or before the photoresist layer is exposed, which is referred to as patternless inspection.
10. Wafer Probe Test
The wafer probe test is a pin test of each die on the manufactured wafer. During the test, the wafer is fixed on a vacuum suction chuck. Hair-like probes are in contact with every solder joint on the chip. During the testing process, the electrical performance and circuit function of each chip is detected. Unqualified grains will be marked, and then when the chip is cut into independent chip particles, the marked unqualified chip particles will be eliminated. Relevant data from probe detection can now be used to help improve yield in wafer manufacturing.
11. Packaging (Assembly & Packaging)
Figure 9 Wafer package
The packaging technology has developed very fast in recent years, mainly because (a) The complexity of the chip is getting higher and higher: the number of transistors contained in the chip has increased sharply, and the pins have also increased. New packaging technologies are needed to meet these needs. (b) Miniaturization of electronic products: Today's electronic products require small size, powerful functions, and low power consumption, which also means higher requirements for wire bonding, and the packaging form must adapt to these changes.
The chips on the wafer are cut into individual chips and then packaged so that the chips can eventually be placed on the PCB. The equipment needed here includes wafer dicing machines, die-attach machines (package chips into lead frames), wire bonders (responsible for connecting chips and lead frames, such as gold wire bonding and copper wire bonding). Different types of wires are used in the wire bonding process: gold (Au), aluminum (Al), copper (Cu). Each material has its advantages and disadvantages and is bonded by different methods. With the emergence of multi-layer packaging and even 3D packaging applications, the demand for ultra-thin wafers is also increasing.
12. Final Test
Because the final chip yield cannot reach 100%, the inspection of the chip becomes more important. How to detect high-performance chips and how to quickly detect them are very important. Considering that each chip needs to be inspected, the fab must balance costs across the board. This has led to the new generation of testing equipment with more powerful inspection functions, lower costs, and faster inspection speeds.