In high-speed PCB design, the via design is an important factor, which consists of the hole, the pad area around the hole, and the POWER layer isolation area . In the process of PCB design, through the analysis of the parasitic capacitance and parasitic inductance of the via, some precautions in the design of high-speed PCB vias are summarized.
Keywords: via; parasitic capacitance; parasitic inductance; non-through-via technology
At present, the design of high-speed PCB is widely used in communication, computer, graphics and image processing and other fields. All high-tech value-added electronic product designs are pursuing the characteristics of low power consumption, low electromagnetic radiation, high reliability, miniaturization and light weight. To achieve the above goals, via design is an important factor in high-speed PCB design.
1. Via Via is an important factor in the design of
multi-layer PCB factory. A via is mainly composed of three parts, one is the hole; the other is the pad area around the hole; the third is the POWER layer isolation area. The process of the via hole is to coat a layer of metal on the cylindrical surface of the hole wall of the via hole by chemical deposition to connect the copper foils that need to be connected in the middle layers, and the upper and lower sides of the via hole are made into ordinary pads. The shape can be directly connected with the lines on the upper and lower sides, or not connected. Vias can be used to electrically connect, fix or position devices.
Vias are generally divided into three categories: blind vias, buried vias and through vias.
Blind holes, which are located on the top and bottom surfaces of the printed circuit board, have a certain depth and are used for the connection of the surface circuit and the underlying inner circuit. The depth of the hole and the diameter of the hole usually do not exceed a certain ratio.
Buried holes refer to connection holes located in the inner layer of the printed circuit board, which do not extend to the surface of the circuit board.
Both blind holes and buried holes are located in the inner layer of the circuit board, and are completed by the through hole forming process before lamination. During the formation of the via hole, several inner layers may be overlapped.
Through-holes, which pass through the entire circuit board, can be used for internal interconnections or as mounting holes for components. Because the through hole is easier to realize in the process and the cost is lower, the
through hole is generally used in the printed circuit board. The classification of vias is shown in Figure 2.
2. Parasitic capacitance
of vias The vias themselves have parasitic capacitances to the ground. If the diameter of the isolation holes of the vias on the ground layer is D2, the diameter of the via pads is D1, the thickness of the PCB is T, and the board substrate is The dielectric constant is ε, the parasitic capacitance of the via is approximated as:
The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. The smaller the capacitance value, the smaller the impact.
3. Parasitic inductance
of vias Parasitic inductance exists in vias themselves. In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than the influence of parasitic capacitance. The parasitic series inductance of the via will weaken the effect of the bypass capacitor and reduce the filtering effect of the entire power system. If L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center drilled
hole, the parasitic inductance of the via is approximately:
It can be seen from the formula It can be seen that the diameter of the via has less influence on the inductance, while the length of the via has the greatest influence on the inductance.
4. Non-penetrating via technology
Non-penetrating vias include blind vias and buried vias.
In the non-through via technology, the application of blind vias and buried vias can greatly reduce the size and quality of the PCB, reduce the number of layers, improve electromagnetic compatibility, increase the characteristics of electronic products, reduce costs, and also make the design work more Simple and fast. In traditional PCB design and processing, through-holes present many problems. First of all, they occupy a large amount of effective space, and secondly, a large number of through holes are densely packed in one place, which also causes huge obstacles to the inner layer routing of multi-layer PCBs. These through holes occupy the space required for routing, and they densely pass through power and ground. The surface of the wire layer will also destroy the impedance characteristics of the power ground wire layer, making the power ground wire layer ineffective. And conventional mechanical drilling will be 20 times the workload of using non-penetrating hole technology.
In PCB design, although the size of pads and vias has been gradually reduced, if the thickness of the board layer is not proportionally reduced, the aspect ratio of the vias will increase, and the increase in the aspect ratio of the vias will reduce reliability. With the maturity of advanced laser drilling technology and plasma dry etching technology, it is possible to apply non-penetrating small blind holes and small buried holes. If the hole diameter of these non-penetrating holes is 0.3mm, the parasitic parameters brought by them are The original conventional hole is about 1/10, which improves the reliability of the PCB.
Due to the use of non-through-via technology, there will be few large vias on the PCB, thus providing more space for traces. The remaining space can be used for large area shielding to improve EMI/RFI performance. At the same time, more remaining space can also be used for the inner layer to partially shield the device and key network cables, so that it has the best electrical performance. The use of non-through vias makes it easier to fan out device pins, making high-density pin devices (such as BGA packaged devices) easy to route, shortening the length of connections, and meeting the timing requirements of high-speed circuits.
5. Selection of vias
in ordinary PCBs In ordinary PCB design, the parasitic capacitance and parasitic inductance of vias have little effect on PCB design. For 1-4 layer PCB design, 0.36mm/0.61mm/1.02mm ( The via holes of drilling/pad/POWER isolation area) are better. Some signal lines with special requirements (such as power lines, ground lines, clock lines, etc.) can use 0.41mm/0.81mm/1.32mm vias, or Select vias of other sizes according to the actual situation.
6. Via design in high-speed PCB
Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. effect. In order to reduce the adverse effects caused by the parasitic effect of the via hole, we can try our best to do it in the design:
(1) Select a reasonable via hole size. For multi-layer PCB design with general density, it is better to use 0.25mm/0.51mm/0.91mm (drilling/pad/POWER isolation area) vias; for some high-density PCBs, 0.20mm/0.46 mm/0.86mm vias, you can also try non-through vias; for power or ground vias, you can consider using a larger size to reduce impedance;
(2) The larger the POWER isolation area, the better, consider the size of the vias on the PCB. The density of vias is generally D1=D2+0.41;
(3) The signal traces on the PCB should not be changed as much as possible, that is to say, the vias should be minimized;
(4) The use of thinner PCBs is beneficial to reduce the size of the vias. Two kinds of parasitic parameters;
(5) The pins of power supply and ground should be made with holes nearby. The shorter the leads between the holes and the pins, the better, because they will lead to the increase of inductance. At the same time, the leads of the power supply and the ground should be as thick as possible to reduce the impedance;
(6) Some ground vias are placed near the vias of the signal switching layer to provide a short-distance loop for the signal.
Of course, specific problems need to be analyzed in detail when designing. Considering both cost and signal quality, in high-speed PCB design, designers always hope that the via hole is as small as possible, so that more wiring space can be left on the board. The parasitic capacitance is also smaller, which is more suitable for high-speed circuits. In high-density PCB design, the use of non-penetrating vias and the reduction of vias size also bring about an increase in cost, and the size of vias cannot be reduced indefinitely. It is affected by PCB manufacturers' drilling and electroplating processes. Due to technical limitations, balanced consideration should be given to the via design of high-speed PCBs.