For a long time, I want to write some basic knowledge about PCB routing. A large part of the work of signal integrity is based on the setting of PCB routing rules and routing optimization. The simulation work or post-imitation work is based on the fact that the PCB design has been finalized, that is to say, the related risks of the link have been fixed. Therefore, setting rules to manage risk is more important than risk resolution. The ability to prevent and control is an essential basic skill for future signal integrity engineers.
To prevent and control the risk of PCB routing, the most basic knowledge is to be familiar with common routing rules. The mind map of this article:
01 Length Matching
01. Total line length matching & layered line length matching
The 5 mils matching the total line length has been applied in many product designs, which is also mentioned in many design guidelines.
The concept of layered line length matching does not seem to be so common. The differential line is routed. The BGA area is drilled to the inner layer, and the inner layer wiring is drilled to the terminal. The inner layer impedance is relatively easy to control and the differential line is symmetrical. Therefore, in general, the distance between the two sections of the surface layer is relatively short, so the length matching is generally carried out on the inner layer, that is, the layered line length matching is indirectly implemented. Many times, this concept of layered line length matching is ignored in the design of many products.
02. Nearby compensation
When length mismatches occur, nearby compensation is recommended to prevent discontinuous propagation. How to match the nearest length, the classification of products is different, and the requirements are also different. Consumer products do not give relevant suggestions, but only give relevant suggested values for the BREAKOUT area and the PIN area of the connector.
Some routing methods for the nearest compensation:
03. Match the style
Common matching styles include serpentine lines, routing in the PAD area, etc. The 3W2S principle in serpentine lines is a commonly used winding method in many product designs. Through such operations, line length matching can be achieved.
3W2S is somewhat interrelated, so it is recommended to clarify. Compared with 3W2S deliberately routing to achieve line length matching, the way of routing matching in the PAD area has less impact on matching.
It should be noted that the ultimate goal of line length matching is isochronous.
The thinning and lightness of high-speed products, the thickness of the PCB limits the number of wiring layers, and there are high-speed lines running on two adjacent layers. In order to reduce mutual crosstalk, the wiring method has spacing control (the DDR part is more difficult to implement), Vertical wiring (this method is more difficult to implement), 30-degree angle wiring (this method is recommended).
Double-belt lines are a major trend in future product design, and there are many details, such as the parallel repeatability and length of double-belt lines.
03 Differential Transitional Via
PCB traces and vias are an indispensable part. We don't talk about blind and buried vias here, only differential vias are dealt with.
Different products have different design rules, but they are generally the same:
1. If the differential via stub (stump) is long and the signal rate is relatively high (such as PCIe 4.0), backdrill is required;
2. If the reference layer is converted from differential vias, a return ground hole should be drilled. The distance from the ground hole to the VIA should be greater than the differential via distance itself, and the ground hole should be within 100 mils.
Speaking of stub (stump), there is also a U-turn move, which will be used in the terminal THM connector.
04 Component Footprint Plane Voiding
The devices mentioned here are not only Electrostatic Diode (ESD) and Common-mode choke (CMC) used in USB, but also matching resistors in high-speed links, coupling capacitors, and SMT connectors. Optimizing it is to reduce abrupt changes in impedance.
The way to optimize the processing is to perform voiding on the adjacent plane layers.
The above is an example of a simple high-speed link path to list the common rules related to PCB routing. Of course, there will be different rules for different products, and the same goal is achieved. All the rules are to reduce crosstalk, reflection, loss, etc., to ensure signal integrity. If some rules contradict each other, the signal integrity engineer needs to make a choice and give a reasonable solution at this time.