Reducing signal degradation requires dielectrics with lower Dk and LT, more metal and conductors without rough surfaces.

At a trade show a few years ago, our booth was next to a booth with a very loud demonstration transferring 112Gbps over a distance of about one meter through cables. I don’t know how many terabytes of data they transferred during the show, but the demonstration equipment was noisy because of the industrial cooling equipment. I could feel the heat coming out of it. The devices were transferring data and not much else. How much energy is required to transmit data, and why is so much power dissipated into heat, I wondered.

PCB interconnects degrade digital signals. Signals may be reflected, coupled to other interconnects, or to power distribution structures or free space, but most important, conductors and dielectrics always absorb the signal energy and dissipate or turn it into heat. This article is about signal degradation due to the inevitable absorption and dispersion caused by dielectrics and conductors. How much energy does it take to transmit one bit of information, and where does this energy eventually go?

*All*signal energy is converted into heat.

For a 50Gbps NRZ signal with 20ps unit interval, the energy converted into heat in a differential link with termination resistors is about 0.4pJ/bit (20mW x 20psec – product of power and bit time). This is practically an immutable bottom level. We cannot reduce the energy per bit in the copper interconnects under the assumptions provided above (1V, 100Ω). 20mW of power or 0.4pJ/bit for 50Gbps NRZ signal – is it small or not? It would take almost 929 hours to boil one cup of water. (Heat 200g of water from 20 to 100°C.) Admittedly, it does not look like much heat. However, this is just one link, and internet routers or switches may have more than 1,000 such links. That is enough to have a cup of tea in about an hour. This is still not impressive.

But this is not the end of the story. When equalization is included, the actual cost of a bit transfer on a PCB for 50Gbps is at least an order of magnitude larger. It is about 5pJ/bit (or 250mW) for 50Gbps NRZ.^{1} With a thousand links, this is enough to prepare a cup of tea in five minutes, and the IOs on chip dissipate about 90% of this energy.

Does this explain the industrial cooling equipment for 112Gbps links? I haven’t seen the power consumption data for 112Gbps or the upcoming 224Gbps links. (Email me if you have it.) But, following the recent trends (doubling data rate increases required power by 30%), it should be about 6.5pJ/bit (325mW) for 112Gbps and 8.45pJ/bit (422mW) for 224Gbps.

The number of IOs does not increase at the same time. That may be the clue. Also, the prototype equipment may be much less efficient. On the bright side, some recent developments in this area promise to reduce the numbers to about 2pJ/bit or 100mW^{2}.

Why do we need so much power? To mitigate the signal degradation in interconnects between the driver and receiver. Transmitters and receivers are not two transistor devices in serial interconnects; they contain hundreds (maybe thousands) of transistors, and most of the energy is spent generating and restoring the signal. Can we reduce the power by design of interconnects? The answer is absolutely yes – by reducing the signal degradation in interconnects!

At DesignCon 2020^{3}, we discussed the major signal degradation factors and how to reduce them or design “transparent” or “clean” interconnects. The degradation factors can be broken into three categories: 1) absorption or dissipation by conductors and dielectrics and dispersion related to that; 2) reflections; and 3) coupling.

We called the first category “thermal losses” because the signal energy is literally heating the interconnect materials. Though, maybe “absorption” or “dissipation losses” are better terms.

When performing interconnect modeling, the following questions should be answered: What effects are important at a particular data rate? Does signal integrity software account for them? If all effects are included, will the model correlate with measurements?

^{4}The signal energy location can be illustrated with the peak power density flow (PDF), a vector product of electric and magnetic fields. For a typical PCB stripline interconnect (FIGURE 3), the color scale is used to plot peak power flow density (PFD) in W/m^2 (shown in dB), computed with Simbeor THz.

^{2}It is important to understand this.

In general, dielectric properties can be described with the permittivity that is a complex function of frequency – always for real materials! We call the real part of the permittivity the dielectric constant (Dk). The ratio of the negative imaginary part of permittivity to the real part is called loss tangent (LT) or dissipation factor (DF). It describes the power loss to heat and dispersion. A universal dielectric model may look like the one in FIGURE 4.

The conduction losses for the dielectric materials in the PCB and packaging dielectrics are negligibly small. They are responsible for the increase of the imaginary part below 100Hz. (This is not a typo.) There are very few free charges in the dielectrics, such as ionic carriers.

At frequencies up to 1THz, we are dealing with the relaxation of losses related to electronic polarization of atoms (RC circuit type – no oscillations). That is modeled as either multipole Debye or wideband Debye models4. That also means the Dk can only decrease with the frequency at these frequencies. We are dealing with composite solids here, mostly polymers. Lorentzian terms (oscillating RLC circuit type) are added for illustrative purposes to show the resonant properties of the solid PCB materials are important over 1THz, where Dk may go down because of the resonances.

A causal wideband Debye model is used here.^{5} It can be defined with Dk and LT at one frequency point: 1GHz in this case. The model analytically defines the dielectric constant and loss tangent dispersion from 0 up to 100GHz. The model is causal and includes the dispersion (change in Dk with frequency) of the phase delay and characteristic impedance, as illustrated in FIGURE 6.

It also demonstrates that dielectrics with high losses (typically FR-4) have much higher dispersion compared to the ultra-low-loss dielectrics that do not show much dispersion at the frequencies important for analysis of multi-gigabit interconnects. This is not only for the frequency-dependent losses; phase dispersion also causes signal degradation. Signal harmonics are attenuated more at high frequencies and travel with different velocities as well.

^{5}and in “How Interconnects Work: Modeling Conductor Loss and Dispersion.”

^{6}Conductor absorption and dispersion effects are summarized and illustrated in FIGURE 7.

Though conductors are an indispensable part of PCB interconnects – with no viable alternatives so far – additional unavoidable losses and dispersion are related to them. In the case of dielectrics, the absorption can be illustrated with the losses per meter, as shown in FIGURE 8.

Even with smooth copper, the conductor losses may exceed the dielectric losses for the ultra-low-loss dielectric (valid for a particular cross-section), meaning the minimum possible losses on a PCB are limited mostly by the copper and copper roughness. To have the losses on the PCB closer to cables over a similar bandwidth, larger, smooth traces must be used, reducing current density and overall losses. As a result of the causality requirements, the conductor losses cause dispersion of the phase delay and characteristic impedance, as illustrated in FIGURE 9.

^{6,7}

What about the predictability of the absorption or dissipation losses and dispersion? In other words, how do we build models that correlate with the measurements? It depends on availability of the frequency-continuous ultra-broadband models for dielectric and conductor roughness.

Dielectric data from laminate manufacturers can be used to construct such models with sufficient accuracy for preliminary analysis or lower data rates. (They can be defined with a numerical experiment).^{5} Dielectric models for higher data rates and better accuracy must be extracted from measurements. Parameters for conductor roughness models are usually not available and always must be extracted from measurements. Identification with GMS-parameters^{8} or SPP light^{9} techniques with a separation of dielectric and conductor losses can be used to build dielectric and conductor roughness models.

- Use dielectrics with lower Dk and LT.
- Use more metal to reduce current density. (Wider interconnect traces absorb less energy.) (This is subject to single-mode propagation limit.)
- Use conductors without roughness or “engineered” rough surfaces without additional losses.

Generated signal energy is always turned into heat in conductors, dielectrics or termination resistors, no matter what we do with the interconnect losses. However, interconnects with lower losses reduce the energy required for signal conditioning and restoration. This is valid under one important condition: very low reflections and no coupling.