Signal coupling problems occur when a PCB trace with high impedance termination is next to a trace with fast-changing voltages such as a digital or clock signal. It only takes two traces to build this easy-to-construct PCB capacitance. And the cause of this noise is high-speed signals such as digital level shifts with a fast change in voltage over time (¶V/¶t) and a high impedance trace.
Figure 1 diagrams two PCB traces; 0.003 mm or “d” is the distance between the traces and “L” is the adjoining length.
Figure 1 Use PCB trace thickness (w), distance (d), and length (L) dimensions to determine the capacitance between two traces.
The dielectric constant of air (eo) and dielectric constant of er—which depends on the glass weave style, thickness, resin content, and copper foil roughness of the substrate coating around the traces—complete the final formula for your new capacitor.
A case of this type of PCB capacitor is shown below as Example 1:
L = 1 inch or 25.4 mm
d = 0.2 mm
w = 0.003 mm
eo = 8.85 x 10-12 F/m
er = 4.8 (FR4 PCB material)
The new capacitor is shown in Equation 1 below:
This capacitance value seems small, but let’s look at the digital and analog signal consequences.
Extrinsic trace capacitance noise
When one trace has a digital clock signal, the signal couples over to other traces as a current instead of voltage. The critical clock characteristic is that the trace’s digital signal has a fast rise and fall time. Another condition is that the receiving trace has a high impedance termination such as the input to an amplifier in a buffer configuration (Figure 2).
Figure 2 If the rise and fall times on the voltage CLK trace has a fast change in voltage with time, a signal appears as current spikes on the second trace. A guard trace disrupts the e-field and attenuates the coupling phenomena. Source: Texas Instruments
The magnitude of the second trace’s current spike depends on the trace-to-trace capacitance and the second trace’s terminating resistance magnitude.
Taking Example 1 a step forward to Example 2:
RIN = 1013W (op amp input impedance)
C = 0.0162 x 10-12 Farads (PCB capacitance)
¶V/¶t = (3.3 x 0.8 V)/230 ps = 11. 5 x 109 V/sec (100-MHz clock)
The peak voltage at the output of the op amp is shown in Equation 2 below:
A 1.86 GV overdrive to the input of the op amp is overly significant. It looks like the circuit is dead-on-arrival. However, there are some design techniques that we can use to bring this circuit back to life.