How to avoid the negative effects of vias in high-speed PCB design

The basic concept of vias

Via is an important part of multilayer PCB. The cost of drilling usually accounts for 30% to 40% of the cost of PCB. Simply put, each hole on the PCB can be called via. From a functional point of view, vias can be divided into two categories: one is used as an electrical connection between layers, the other is used for fixing or positioning devices. In terms of technology process, these vias are generally divided into three categories, namely blind vias, buried vias, and through-hole. The blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used for the connection between the surface layer circuit and the inner layer circuit below. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, it will not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board, which is completed by a through-hole molding process before lamination, and several inner layers may be overlapped during the formation of the via hole.


The third type is called a through-hole. This hole penetrates the entire circuit board and can be used for internal interconnection or as a component positioning hole. Because the through-hole is easier to implement in technology and lower in cost, most printed circuit boards use it instead of the other two vias. The vias mentioned below are considered as through-holes unless otherwise specified.

From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via, the better, so that more wiring space can be left on the board. In addition, the smaller the via, the smaller of the parasitic capacitance of its own, the more suitable for high-speed circuits. However, the reduction of the hole size also brings an increase in cost, and the size of the via hole cannot be reduced without limit. It is limited by drilling and plating (plating) and other process technologies. The smaller the hole is , the longer time the hole takes, the easier it is to deviate from the center. And when the depth of the hole exceeds 6 times the diameter of the drill hole, there is no guarantee that the hole wall can be evenly plated with copper. For example, if the thickness (through-hole depth) of a normal 6-layer PCB is 50Mil, then under normal conditions, the minimum drilling diameter that PCB manufacturers can provide is only 8Mil. With the development of laser drilling technology, the size of the drill hole can also become smaller and smaller. Generally, a via with a diameter of 6 Mils or less is called a micro hole. Micro-holes are often used in HDI (High Density Interconnect Structure) design. Micro-hole technology can allow vias to directly hit the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.

Vias appear as discrete breakpoints in impedance on the transmission line, which can cause signal reflections. In general, the equivalent impedance of a via hole is about 12% lower than that of a transmission line. For example, when a 50 ohm transmission line passes through a via, the impedance will be reduced by 6 ohms (specifically related to the size of the via and the thickness of the board, not absolute reduction). However, the reflection caused by the discontinuous impedance of the via hole is actually very small. The reflection coefficient is only: (44–50)/(44+50)=0.06. The problems caused by the via hole are more concentrated on the impact on the parasitic capacitance and inductance.

Parasitic capacitance and inductance of vias

The via itself has parasitic stray capacitance. If the diameter of the solder mask on the ground layer of the via is known to be D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate Is ε, then the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)


The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50Mil, if the diameter of the via pad used is 20Mil (the diameter of the drill hole is 10Mils) and the diameter of the solder mask area is 40Mil, then we can approximate the parasitic capacitance of the via via the above formula: C=1.41x4.4x0.050x0.020/(0.040–0.020)=0.31pF. The variation of the rise time caused by this part of capacitance is roughly: T10–90=2.2C(Z0/2)=2.2x0 .31x(50/2)=17.05ps

It can be seen from these values ??that although the effect of slowing the rise delay caused by the parasitic capacitance of a single via is not very obvious, if multiple vias are used in the trace to switch between layers, multiple vias will be used , careful design should be considered. In actual design, the parasitic capacitance can be reduced by increasing the distance between the via and the copper area (Anti-pad) or reducing the diameter of the pad.

Through the presence of parasitic capacitance in the via, there is also parasitic inductance. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the via is often greater than the effect of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following empirical formula to simply calculate the approximate parasitic inductance of a via: L=5.08h[ln(4h/d)+1]. The L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has little effect on the inductance, and the length of the via has the greatest impact on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance size It is: XL=πL/T10–90=3.19Ω. Such impedance cannot be ignored when passing high-frequency currents. It is important to note that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so that the parasitic inductance of the vias will multiply increased.

How to use vias

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, the seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, in the design, you can do as much as possible:


1. From the two aspects of cost and signal quality, choose a reasonable size of via size. If necessary, you can consider using different sizes of vias. For example, for power or ground vias, you can consider using larger sizes to reduce impedance. For signal traces, you can use smaller vias. Of course, as the via size decreases, the corresponding cost will increase.

2. The two formulas discussed above can be concluded that the use of thinner PCB boards is beneficial to reduce the two parasitic parameters of vias.

3. The signal traces on the PCB board should not change layers as much as possible, that is to say, try not to use unnecessary vias.

4. The power and ground pins should be drilled through the hole. The shorter the lead between the hole and the pin, the better. You can consider making multiple vias in parallel to reduce the equivalent inductance.

5. Place some grounded vias near the vias for signal changeover to provide the closest loop for the signal. You can even place some extra ground vias on the PCB.

6. For high-density high-speed PCB boards, consider using micro vias.