[Power Management] How to achieve the best DCM flyback converter design?

The flyback converter can operate in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). But for many low-power and low-current applications, DCM flyback converters are more compact and less expensive. This article details the design steps for such a converter.

A characteristic of DCM operation is that the converter's rectifier current decreases to zero before the next switching cycle begins. Reducing the current to zero before switching will reduce dissipation in the field-effect transistor (FET) and reduce rectifier losses, and will generally reduce transformer size requirements.

CCM operation, on the other hand, maintains current conduction in the rectifier until the end of the entire switching cycle. We have introduced the design considerations of flyback converters and CCM in the two articles "Several Key Design Considerations for Flyback Converters" and "Design Details and Loss Calculation of CCM Flyback Converters" Power stage formula for flyback converter. CCM operation is best for medium to high power applications, but if it is a low power application, you can use a DCM flyback converter, please continue reading below.

Figure 1 shows a simplified flyback schematic that can operate in DCM or CCM mode and switch between modes based on timing. In order to keep the circuit operating in DCM mode, as will be evaluated in this article, the switching waveforms of the key components should have the characteristics shown in Figure 2.

During the duty cycle period D, FET Q1 is turned on and the circuit starts working. The current in the primary winding of T1 always starts from zero and rises to a peak value determined by the inductance of the primary winding, the input voltage and the on-time t1. During this FET on-time, diode D1 is reverse biased by the polarity of the secondary winding of T1, forcing all output current to be supplied by output capacitor COUT during t1 and t3.

Figure 1: Simplified flyback converter schematic that can operate in DCM or CCM mode

When Q1 turns off during period 1-D, T1's secondary voltage reverses polarity, allowing D1 to conduct current to the load and charge COUT. The current in D1 decreases linearly from its peak value to zero during t2. Once the energy stored in T1 is exhausted, only ringing remains for the remaining time period t3. This ringing is primarily caused by the magnetizing inductance of T1 and the parasitic capacitances of Q1, D1, and T1. This is easily seen by the drain voltage of Q1 during t3, which drops from VIN plus the reflected output voltage back to VIN, since T1 cannot support the voltage once the current is cut off. (Note: Without enough dead time in t3, it is possible to enter CCM operation.) The currents in CIN and COUT are the same as the currents in Q1 and D1, but there is no DC offset.

The shaded areas A and B in Figure 2 highlight the transformer's volt microsecond products during t1 and t2, which must remain balanced to prevent saturation. Area "A" represents (Vin/Nps)×t1, while "B" represents (Vout+Vd)×t2, both with the secondary side as reference. Np/Ns is the turns ratio between the primary side and the secondary side of the transformer.

Figure 2: Key voltage and current switching waveforms for a DCM flyback converter and several key parameters that the designer must specify.

Table 1 details the characteristics of DCM relative to CCM. A key attribute of DCM is that having lower primary inductance reduces the duty cycle regardless of the transformer turns ratio. It allows you to limit the maximum duty cycle of your design. This may be important if you want to use a specific controller or stay within specific on or off time limits. Lower inductance requires lower average energy storage (albeit with higher peak FET current) and generally allows the use of smaller transformers compared to CCM designs.

Another advantage of DCM is that this design eliminates the D1 reverse recovery losses in a standard rectifier since the current is zero at the end of t2. Reverse recovery losses typically manifest themselves as increased dissipation in Q1, so eliminating them reduces the stress on the switching transistor. This advantage becomes more apparent at higher output voltages, since the reverse recovery time of the rectifier also increases with the diode voltage rating.