For simple electronic devices, even if the PCB design is wrong, the circuit can still work properly. However, for complex electronic devices, especially those with smaller size, faster operation and lower power consumption, the circuit has a low error tolerance rate. At this time, PCB design will be very important. Ground bounce is a problem that is easily overlooked. The following explains what ground bounce is and how to avoid ground bounce in PCB design.
What is ground bounce?
When the PCB ground voltage is different from the chip die package ground voltage, a kind of noise generated during transistor switching is called ground bounce. To understand the concept of ground bounce, let's take a push-pull circuit as an example. The push-pull circuit can provide a logic low or logic high output. It consists of two MOSFETs. The source of the upper p-channel MOSFET is connected to Vss and the drain is connected to the output pin. The drain of the lower n-channel MOSFET is connected to the output pin, and its source is grounded.
Figure 1: Push-pull circuit
The two types of MOSFETs respond oppositely to gate voltage. A logic low signal applied to the gate causes the p-channel MOSFET to connect Vss to the output, while the n-channel MOSFET disconnects the output from Gnd. A logic high signal applied to the gate causes the p-channel MOSFET to disconnect its Vss from the output, while the n-channel MOSFET connects the output to Gnd.
Inside the chip, the die pads are connected to the chip package pins using tiny bond wires with a small amount of inductance, as shown in the model in Figure 1. The circuit also has a certain amount of resistance and capacitance, which are not shown in the figure. The equivalent circuit of a full-bridge switch has three inductors, which represent the inherent inductance of the chip package, and the output is connected to other components.
Assume that the chip input remains at a logic low level for a period of time, and the upper transistor connects the circuit output to Vss through the upper MOSFET. After a certain period of time, there will be a stable magnetic field in LO and LA, and the potential difference between AVO, △VA and OVB is 0 volts. The wires store a small amount of charge. Once the input logic switches to a high level, the upper MOSFET disconnects Vss from the output, and the lower gate triggers the lower MOSFET to connect the circuit output to GND. This means that when the input logic changes, the entire system also changes.
Causes of Ground Bounce
The potential difference between the output and ground causes current to flow from the output to ground through the lower MOSFET. The inductor uses the energy stored in its magnetic field to establish a potential difference between OVO and △VB, which tries to resist the change in magnetic field. Even though they are electrically connected, the potential difference between the output and ground is not immediately 0V. Note that the output was previously at Vss and the power supply of MOSFETB was previously at 0V potential. The previous potential difference will cause current to flow as the output line discharges.
At the same time that current begins to transfer from the output to ground, the inductive properties of the package create a potential difference between AVB and AVO in an attempt to maintain the previously established magnetic field. Inductors LB and LO change the source and drain potentials of the MOSFET. This is a problem because the MOSFET gate voltage is referenced to the ground of the die package. When the circuit oscillates around the gate trigger threshold, the input voltage may no longer be sufficient to keep the gate open or turn it on multiple times. When the circuit switches again, similar conditions will cause a potential to be established on OVA, thereby reducing the source voltage of MOSFET A below the trigger threshold.
Effects of Ground Bounce
At the moment the input changes state, the output and MOSFET are no longer in a defined state. The result can be an erroneous switch action, or both turning on at the same time. In addition, any other parts of the die connected to Gnd and Vss will be affected by the switching action. Ground bounce is not just an effect on the die. Just as AVB forces the MOSFET source potential to be above 0V, it forces the circuit Gnd
potential to be below 0V. If multiple gates are actuated simultaneously, the effects of ground bounce become compounded and can completely destroy the circuit.
The following example illustrates the effects of ground bounce. Figure 2 shows Gnd and Vss ground bounce, the signal from a BeagleBone Black. About 1V of noise is generated on the 3.3V line during the switching action, and the signal line continues to resonate before finally falling into the background line noise.
Figure 2: Signals on the BeagleBone Black
The gate is connected to the chip power pins, and the PCB usually shares common power and ground rails. This means that noise can easily be transmitted to other locations in the circuit through the direct electrical connection between Vss and the die ground or coupling through PCB traces.
Figure 3: Image captured from BeagleBone Black
In Figure 3, channel 2 (blue) shows ground and Vss bounce on the undamped signal line. The problem is so severe that it propagates to a different signal line through channel 1 (yellow)
Methods to reduce ground bounce from PCB design
Method 1: Use decoupling capacitors to limit ground bounce. The preferred solution to reduce ground bounce is to install SMD decoupling capacitors between each power rail and ground, as close to the chip as possible. Decoupling capacitors have long traces, which increase inductance, so they are close to the chip. When the die transistor is in the switching state, they will change the potential of the die transistor and the power rail.
Decoupling capacitors provide a temporary low-impedance stable potential for the chip and limit ground bounce so that it does not spread to the rest of the circuit. By keeping the capacitor close to the IC, the inductive loop area in the PCB trace can be minimized and interference can be reduced.
Circuit schematics usually do not show decoupling capacitors, and data sheets will not mention them. This does not mean that the design does not need them. Decoupling capacitors are considered to be the basis of a successful design, and the schematic does not show them only to reduce confusion. If the data sheet does not indicate, 100nf (0.1μF) X7R or NP0 ceramic capacitors are usually selected.
Mixed-signal chips usually have separate analog and digital power pins. Decoupling capacitors should be installed on each power input pin. The capacitor should be located between the chip and multiple vias connected to the PCB power plane.
Decoupling capacitors should be connected to the power plane by vias
It is better to use multiple vias, but this is usually not possible due to board size requirements. If possible, use copper pours or teardrops to connect the vias.
IC (U1) and pads for four capacitors (C1, C2, C3, C4). C1 and C2 are decoupling capacitors for high frequency interference. According to the data sheet, sometimes decoupling capacitors cannot be placed near the IC. If they are far away from the chip, an inductive loop is formed, which makes the ground bounce problem worse. In this case, the decoupling capacitors can be placed on the other side of the board.
Method 2: Use resistors to limit current. Using a series current limiting resistor prevents excessive current from flowing through the IC. This not only helps reduce power consumption and prevent overheating, but also limits the current from the output line through the MOSFET to Vss and Gnd, thereby reducing ground bounce.
Method 3: Reduce inductance through routing. Keep return paths (return paths) of adjacent traces or adjacent layers as much as possible. Due to material reasons, the distance between layer 1 and layer 3 is usually several times the distance between layer 1 and layer 2. Any unnecessary isolation between the signal and the return path will increase the inductance and ground bounce of the signal line.
PCB layout for Arduino Uno
The board above has separate ground return pins for analog and digital. However, the board layout does not isolate the two grounds. There is no clear and direct path between the digital ground pin of the chip and the ground pin on the header strip. The signal will travel through the chip to the header pin and return from the ground pin.
Reduce ground bounce through circuit design
As the number of chip gates increases, so will ground bounce. Delay the switching action of the gates as briefly as possible. For example, a design may flash various LEDs at different intervals (1 second, 2 seconds, 3 seconds, etc.) to indicate the state of the design. Ground bounce has the greatest impact on the circuit when all three LEDs switch at the same time. The impact of ground bounce can be mitigated by delaying the LEDs slightly so that the LEDs are not completely synchronized. Introducing a 1ms delay between LEDs is imperceptible but reduces the impact of ground bounce by a factor of 3.